Computing Passive Reduced-Order Models for Circuit Simulation

Benner, Peter; Quintana-Ortí, Enrique S.; Quintana-Ortí, Gregorio

doi:10.1109/PCEE.2004.21

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Computing Passive Reduced-Order Models for Circuit Simulation

Benner, P., Quintana-Ortí, E. S., & Quintana-Ortí, G. (2004). Computing Passive Reduced-Order Models for Circuit Simulation. In Proceedings of the International Conference on Parallel Computing in Electrical Engineering (PARELEC’04) (pp. 146-151).

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Item Permalink: https://hdl.handle.net/11858/00-001M-0000-0024-CF39-6 Version Permalink: https://hdl.handle.net/11858/00-001M-0000-0026-AE46-2

Genre: Conference Paper

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Creators:
Benner, Peter^{1, 2}, Author
Quintana-Ortí, Enrique S.³, Author
Quintana-Ortí, Gregorio³, Author

Affiliations:
1Other publications of the MPI staff, Max Planck Institute for Dynamics of Complex Technical Systems, Max Planck Society, ou_1738149
2TU Chemnitz, ou_persistent22
3Universidad Jaume I, Castellon, Spain, ou_persistent22

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Dates: Date issued: 2004

Publication Status: Issued

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Rev. Type: Peer

Identifiers: DOI: 10.1109/PCEE.2004.21

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Title: International Conference on Parallel Computing in Electrical Engineering (PARELEC’04)

Place of Event: Dresden, Germany

Start-/End Date: 2004-09-07 - 2004-09-10

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Title: Proceedings of the International Conference on Parallel Computing in Electrical Engineering (PARELEC’04)

Source Genre: Proceedings

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Pages: - Volume / Issue: - Sequence Number: - Start / End Page: 146 - 151 Identifier: ISBN: 0-7695-2080-4