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  Formal Verification of a Processor with Memory Management Units

Dalinger, I. (2006). Formal Verification of a Processor with Memory Management Units. PhD Thesis, Universität des Saarlandes, Saarbrücken.

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Item Permalink: https://hdl.handle.net/11858/00-001M-0000-0029-6CA2-4 Version Permalink: https://hdl.handle.net/11858/00-001M-0000-0029-6CA3-2
Genre: Thesis

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Locator:
http://scidok.sulb.uni-saarland.de/volltexte/2006/633/ (Any fulltext)
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Green
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http://scidok.sulb.uni-saarland.de/doku/urheberrecht.php?la=de (Copyright transfer agreement)
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 Creators:
Dalinger, Iakov1, Author           
Paul, Wolfgang2, Advisor
Seidel, Peter Michael2, Referee
Affiliations:
1International Max Planck Research School, MPI for Informatics, Max Planck Society, Campus E1 4, 66123 Saarbrücken, DE, ou_1116551              
2External Organizations, ou_persistent22              

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Language(s): eng - English
 Dates: 20062006
 Publication Status: Issued
 Pages: XVI, 106 p.
 Publishing info: Saarbrücken : Universität des Saarlandes
 Table of Contents: -
 Rev. Type: -
 Identifiers: BibTex Citekey: DalingerPhD06
 Degree: PhD

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