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  Modeling a hardware synthesis methodology in Isabelle

Basin, D. A., & Friedrich, S. (1996). Modeling a hardware synthesis methodology in Isabelle. In J. von Wright, J. Grundy, & J. Harrison (Eds.), Theorem Proving in Higher Order Logics. 9th International Conference, TPHOLs'96 (pp. 33-50). Berlin, Germany: Springer.

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 Creators:
Basin, David A.1, Author           
Friedrich, Stefan1, Author           
Affiliations:
1Programming Logics, MPI for Informatics, Max Planck Society, ou_40045              

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 Abstract: Formal synthesis is a methodology developed at Kent for combining circuit design and verification. We have reinterpreted this methodology in ISABELLE's theory of higher-order logic so that circuits are synthesized using higher-order resolution. Our interpretation simplifies and extends formal synthesis both conceptually and in implementation. It also supports integration of this development style with other synthesis methodologies and leads to techniques for developing new classes of circuits, e.g., recursive descriptions of parameterized circuits.

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Language(s): eng - English
 Dates: 2010-03-121996
 Publication Status: Issued
 Pages: -
 Publishing info: Berlin, Germany : Springer
 Table of Contents: -
 Rev. Type: -
 Identifiers: eDoc: 519575
Other: Local-ID: C1256104005ECAFC-9C402B9EDA7F0239C125646000573DE3-BasinFriedrich96
 Degree: -

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Title: Untitled Event
Place of Event: Turku, Finland
Start-/End Date: 2003-05-14 - 2003-05-18

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Title: Theorem Proving in Higher Order Logics. 9th International Conference, TPHOLs'96
Source Genre: Proceedings
 Creator(s):
von Wright, J., Editor
Grundy, J., Editor
Harrison, J., Editor
Affiliations:
-
Publ. Info: Berlin, Germany : Springer
Pages: - Volume / Issue: - Sequence Number: - Start / End Page: 33 - 50 Identifier: ISBN: 3540615873

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Title: Lecture Notes in Computer Science
Source Genre: Series
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Publ. Info: -
Pages: - Volume / Issue: - Sequence Number: - Start / End Page: - Identifier: -