English
 
User Manual Privacy Policy Disclaimer Contact us
  Advanced SearchBrowse

Item

ITEM ACTIONSEXPORT
  Fast and robust face detection on a parallel optimized architecture implemented on FPGA

Farrugia, N., Mamalet, F., Roux, S., Yang, F., & Paindavoine, M. (2009). Fast and robust face detection on a parallel optimized architecture implemented on FPGA. IEEE Transactions on Circuits and Systems for Video Technology, 19(4), 597-602. doi:10.1109/TCSVT.2009.2014013.

Item is

Basic

show hide
Item Permalink: http://hdl.handle.net/11858/00-001M-0000-000E-B0C4-D Version Permalink: http://hdl.handle.net/11858/00-001M-0000-002B-C082-8
Genre: Journal Article

Files

show Files
hide Files
:
Farrugia_et_al_2009 (Publisher version), 41KB
Name:
Farrugia_et_al_2009
Description:
-
Visibility:
Public
MIME-Type / Checksum:
text/html / [MD5]
Technical Metadata:
Copyright Date:
-
Copyright Info:
-
License:
-

Locators

show
hide
Description:
-

Creators

show
hide
 Creators:
Farrugia, Nicolas1, 2, Author              
Mamalet, Franck1, Author
Roux, Sebastien1, Author
Yang, Fan2, Author
Paindavoine, Michel2, Author
Affiliations:
1Orange Labs, Grenoble, France, ou_persistent22              
2LE2I Laboratory, Dijon, France, ou_persistent22              

Content

show
hide
Free keywords: Embedded; Face detection; FPGA; High level synthesis; Parallel architecture; Realtime
 Abstract: In this paper, we present a parallel architecture for fast and robust face detection implemented on FPGA hardware. We propose the first implementation that meets both real-time requirements in an embedded context and face detection robustness within complex backgrounds. The chosen face detection method is the Convolutional Face Finder (CFF) algorithm, which consists of a pipeline of convolution and subsampling operations, followed by a multilayer perceptron. We present the design methodology of our face detection processor element (PE). This methodology was followed in order to optimize our implementation in terms of memory usage and parallelization efficiency. We then built a parallel architecture composed of a PE ring and an FIFO memory, resulting in a scalable system capable of processing images of different sizes. A ring of 25 PEs running at 80 MHz is able to process 127 QVGA images per second and performing real-time face detection on VGA images (35 images per second).

Details

show
hide
Language(s): eng - English
 Dates: 2008-06-102007-10-252009-03-042009-04
 Publication Status: Published in print
 Pages: -
 Publishing info: -
 Table of Contents: -
 Rev. Method: -
 Identifiers: DOI: 10.1109/TCSVT.2009.2014013
 Degree: -

Event

show

Legal Case

show

Project information

show

Source 1

show
hide
Title: IEEE Transactions on Circuits and Systems for Video Technology
Source Genre: Journal
 Creator(s):
Affiliations:
Publ. Info: -
Pages: - Volume / Issue: 19 (4) Sequence Number: - Start / End Page: 597 - 602 Identifier: ISSN: 1051-8215
CoNE: /journals/resource/954925593490