Grain Boundary Engineering in Copper Through-via Silicon Interconnects

Ratanaphan, S.; Xu, D.; Xu, L.; Raabe, D.; Tu, K.

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Grain Boundary Engineering in Copper Through-via Silicon Interconnects

Ratanaphan, S., Xu, D., Xu, L., Raabe, D., & Tu, K. (2008). Grain Boundary Engineering in Copper Through-via Silicon Interconnects. Talk presented at MRS Fall Conference 2008. Boston, MA, USA. 2008-12-03.

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Item Permalink: https://hdl.handle.net/11858/00-001M-0000-0019-44D9-6 Version Permalink: https://hdl.handle.net/11858/00-001M-0000-0019-44DB-2

Genre: Talk

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Creators:
Ratanaphan, S.¹, Author
Xu, D., Author
Xu, L., Author
Raabe, D.¹, Author
Tu, K., Author

Affiliations:
1Microstructure Physics and Alloy Design, Max-Planck-Institut für Eisenforschung GmbH, Max Planck Society, ou_1863381

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Language(s): eng - English

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Publication Status: Not specified

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Identifiers: eDoc: 395749

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Title: MRS Fall Conference 2008

Place of Event: Boston, MA, USA

Start-/End Date: 2008-12-03

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