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  Sparse Matrix Assembly on the GPU Through Multiplication Patterns

Zayer, R., Steinberger, M., & Seidel, H.-P. (2017). Sparse Matrix Assembly on the GPU Through Multiplication Patterns. In IEEE High Performance Extreme Computing Conference (pp. 1-8). Piscataway, NJ: IEEE. doi:10.1109/HPEC.2017.8091057.

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Item Permalink: https://hdl.handle.net/21.11116/0000-0000-3B33-5 Version Permalink: https://hdl.handle.net/21.11116/0000-0000-3B34-4
Genre: Conference Paper
Latex : Sparse Matrix Assembly on the {GPU} Through Multiplication Patterns

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 Creators:
Zayer, Rhaleb1, Author           
Steinberger, Markus2, Author           
Seidel, Hans-Peter1, Author           
Affiliations:
1Computer Graphics, MPI for Informatics, Max Planck Society, ou_40047              
2External Organizations, ou_persistent22              

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Language(s): eng - English
 Dates: 20172017
 Publication Status: Issued
 Pages: -
 Publishing info: -
 Table of Contents: -
 Rev. Type: -
 Identifiers: DOI: 10.1109/HPEC.2017.8091057
BibTex Citekey: Zayer_HPEC2017
 Degree: -

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Title: IEEE High Performance Extreme Computing Conference
Place of Event: Waltham, MA, USA
Start-/End Date: 2017-09-12 - 2017-09-14

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Title: IEEE High Performance Extreme Computing Conference
  Abbreviation : HPEC 2017
Source Genre: Proceedings
 Creator(s):
Affiliations:
Publ. Info: Piscataway, NJ : IEEE
Pages: - Volume / Issue: - Sequence Number: - Start / End Page: 1 - 8 Identifier: ISBN: 978-1-5386-3472-1