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  Fast All-Digital Clock Frequency Adaptation Circuit for Voltage Droop Tolerance

Függer, M., Kinali, A., Lenzen, C., & Wiederhake, B. (2018). Fast All-Digital Clock Frequency Adaptation Circuit for Voltage Droop Tolerance. In 24th IEEE International Symposium on Asynchronous Circuits and Systems (pp. 68-77). Piscataway, NJ: IEEE. doi:10.1109/ASYNC.2018.00025.

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FKLW18droop.pdf (Preprint), 390KB
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© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works
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 Creators:
Függer, Matthias1, Author
Kinali, Attila2, Author           
Lenzen, Christoph2, Author           
Wiederhake, Ben2, Author           
Affiliations:
1External Organizations, ou_persistent22              
2Algorithms and Complexity, MPI for Informatics, Max Planck Society, ou_24019              

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Language(s): eng - English
 Dates: 20182018
 Publication Status: Published online
 Pages: -
 Publishing info: -
 Table of Contents: -
 Rev. Type: -
 Identifiers: BibTex Citekey: Fuegger_ASYNC2018
DOI: 10.1109/ASYNC.2018.00025
 Degree: -

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Title: 24th IEEE International Symposium on Asynchronous Circuits and Systems
Place of Event: Vienna, Austria
Start-/End Date: 2018-05-13 - 2018-05-16

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Project name : ToRH
Grant ID : 716562
Funding program : Horizon 2020 (H2020)
Funding organization : European Commission (EC)

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Title: 24th IEEE International Symposium on Asynchronous Circuits and Systems
  Abbreviation : ASYNC 2018
  Subtitle : Proceedings
Source Genre: Proceedings
 Creator(s):
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Publ. Info: Piscataway, NJ : IEEE
Pages: - Volume / Issue: - Sequence Number: - Start / End Page: 68 - 77 Identifier: ISBN: 978-1-5386-5883-3