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キーワード:
ATLAS
要旨:
The planned high luminosity upgrade of the Large Hadron Collider (HL-LHC) increases the requirements on radiation hardness of directly exposed electronics. In case of the hadronic end-cap calorimeter (HEC) of ATLAS the electronic,
inside the cryostat, will be exposed to a strongly increased total integrated neutron fluence. Therefore, the HEC group of the Max Planck Institute for Physics (MPP) investigated radiation hardness of different semiconductor technologies.
In this thesis the radiation response of insulated gate field effect transistors (made in SGB25V technology from IHP GmbH) was studied under and after high neutron irradiation. This is motivated by the possibility of enhanced radiation hardness for advanced CMOS technologies with decreased gate oxide thickness. In the experiment transistors with different channel length and width were irradiated with up to 6.7 x 10^15 neutron equivalent (1 MeV)/cm^2 with an energy spectrum ≤ 34 MeV at the cyclotron in Řež (near Prague), Czech Republic. The devices were monitored during the irradiation process and the following two and a half hours beyond. For the post-irradiation measurements other samples were irradiated unpowered and stored at room temperature for more than seven months, and subsequently the dies were measured over a time period of up to three weeks.
The given test structure with a common gate, source and bulk connection required the development of a dedicated threshold voltage extraction using BSIM3. All transistors had to be read-out simultaneously to record the complete drift behavior without influence of previously applied fields. The advantage of the common connection pads are more compact structures. This increased the comparability for all spatial dependent parameters like process variation, temperature or irradiation, and the simultaneous tests reduced the measurement time substantially.
The obtained threshold voltage of a reference from the post-irradiated measurement with constant bias conditions drifts logarithmically similar to the response for ionizing radiation. By alternating between low drain voltages and low gate-drain voltages a difference between the short channel transistors (0.21 μm and 0.24 μm) and the long channel transistors (25 μm) was observed and attributed
to hot carrier injection. The threshold voltage drift for the alternating working condition could be scaled linear for different irradiation fluences. For ten times larger neutron irradiation three to four times larger threshold voltage drift was seen. Also a power law dependence between the gate leakage and the neutron fluence was observed.
Parameter extraction using BSIM3 was realized by minimizing the difference of measurement data and circuit simulation. Although the radiation hardness of the tested devices is not sufficient for use in the HEC of ATLAS, the developed
method could also be directly applied for efficient and low-cost tests of other technologies.
