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Abstract:
Switched capacitor analog memories are well suited to a number of applications where a continuous digitisation of analog signals is not needed. In data acquisition systems based on the use of an analog memory, the input waveforms are sampled and stored at a high rate for a limited period of time, and the analog samples are then retrieved at a lower rate and digitised with a slow ADC before new waveforms are acquired. The advantages of using an analog memory are lower overall power dissipation and cost, high density, and potentially superior dynamic range at high sampling rates. The analog memory shows the fact that the sampling and storage of samples in analog memory cells can be accomplished at a higher rate and with a greater precision than direct digital conversion. This dissertation examines the important components of two analog memories in detail. The research has led to the design of two analog memories that can acquire analog waveforms at sampling rates of several hundred MHz. This is accomplished by a memory architecture in which the memory cell pedestals and sampling times are independent of the signal level. The write address control for these memories has been realised with inverter delay chains that provide high performance with respect to sampling rate and timing accuracy. Based upon the concepts developed in this work, two analog memories were designed and integrated in a AMS 0.8 um CMOS technology with poly-to-poly capacitors. Extensive measurements of these prototypes at a sampling rate of 500 MHz are presented and demonstrate a dynamic range, linearity, offset, and gain accuracy corresponding to a precision of 8 bits after a simple multiplication and addition correction procedure
