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Conference Paper

Modeling a hardware synthesis methodology in Isabelle

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Basin,  David A.
Programming Logics, MPI for Informatics, Max Planck Society;

/persons/resource/persons44446

Friedrich,  Stefan
Programming Logics, MPI for Informatics, Max Planck Society;

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Citation

Basin, D. A., & Friedrich, S. (1996). Modeling a hardware synthesis methodology in Isabelle. In J. von Wright, J. Grundy, & J. Harrison (Eds.), Theorem Proving in Higher Order Logics. 9th International Conference, TPHOLs'96 (pp. 33-50). Berlin, Germany: Springer.


Cite as: https://hdl.handle.net/11858/00-001M-0000-0014-ABEC-A
Abstract
Formal synthesis is a methodology developed at Kent for combining circuit design and verification. We have reinterpreted this methodology in ISABELLE's theory of higher-order logic so that circuits are synthesized using higher-order resolution. Our interpretation simplifies and extends formal synthesis both conceptually and in implementation. It also supports integration of this development style with other synthesis methodologies and leads to techniques for developing new classes of circuits, e.g., recursive descriptions of parameterized circuits.