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Phasemeter core for intersatellite laser heterodyne interferometry: modelling, simulations and experiments

MPG-Autoren
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Gerberding,  Oliver
Laser Interferometry & Gravitational Wave Astronomy, AEI-Hannover, MPI for Gravitational Physics, Max Planck Society;

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Sheard,  Benjamin
Laser Interferometry & Gravitational Wave Astronomy, AEI-Hannover, MPI for Gravitational Physics, Max Planck Society;

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Bykov,  Iouri
Laser Interferometry & Gravitational Wave Astronomy, AEI-Hannover, MPI for Gravitational Physics, Max Planck Society;

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Kullmann,  Joachim
Laser Interferometry & Gravitational Wave Astronomy, AEI-Hannover, MPI for Gravitational Physics, Max Planck Society;

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Delgado,  Juan Jose Esteban
Laser Interferometry & Gravitational Wave Astronomy, AEI-Hannover, MPI for Gravitational Physics, Max Planck Society;

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Danzmann,  Karsten
Laser Interferometry & Gravitational Wave Astronomy, AEI-Hannover, MPI for Gravitational Physics, Max Planck Society;

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Heinzel,  Gerhard
Laser Interferometry & Gravitational Wave Astronomy, AEI-Hannover, MPI for Gravitational Physics, Max Planck Society;

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Zitation

Gerberding, O., Sheard, B., Bykov, I., Kullmann, J., Delgado, J. J. E., Danzmann, K., et al. (2013). Phasemeter core for intersatellite laser heterodyne interferometry: modelling, simulations and experiments. Classical and quantum gravity, 30(23): 235029. doi:10.1088/0264-9381/30/23/235029.


Zitierlink: https://hdl.handle.net/11858/00-001M-0000-0014-A006-A
Zusammenfassung
Inter satellite laser interferometry is a central component of future space-borne gravity instruments like LISA, eLISA, NGO and future geodesy missions. The inherently small laser wavelength allows to measure distance variations with extremely high precision by interfering a reference beam with a measurement beam. The readout of such interferometers is often based on tracking phasemeters, able to measure the phase of an incoming beatnote with high precision over a wide range of frequencies. The implementation of such phasemeters is based on all digital phase-locked loops, hosted in FPGAs. Here we present a precise model of an all digital phase locked loop that allows to design such a readout algorithm and we support our analysis by numerical performance measurements and experiments with analog signals.