Grain Boundary Engineering in Copper Through-via Silicon Interconnects

Ratanaphan, S.; Xu, D.; Xu, L.; Raabe, D.; Tu, K.

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Grain Boundary Engineering in Copper Through-via Silicon Interconnects

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Ratanaphan, S.
Microstructure Physics and Alloy Design, Max-Planck-Institut für Eisenforschung GmbH, Max Planck Society;

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Raabe, D.
Microstructure Physics and Alloy Design, Max-Planck-Institut für Eisenforschung GmbH, Max Planck Society;

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Ratanaphan, S., Xu, D., Xu, L., Raabe, D., & Tu, K. (2008). Grain Boundary Engineering in Copper Through-via Silicon Interconnects. Talk presented at MRS Fall Conference 2008. Boston, MA, USA. 2008-12-03.

Cite as: https://hdl.handle.net/11858/00-001M-0000-0019-44D9-6

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