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Conference Paper

A 130 nm CMOS PLL for Phase-II ATLAS-MDT TDC

MPS-Authors

Pipino,  Alessandra
Max Planck Institute for Physics, Max Planck Society and Cooperation Partners;

Matteis,  Marcello De
Max Planck Institute for Physics, Max Planck Society and Cooperation Partners;

Resta,  Federica
Max Planck Institute for Physics, Max Planck Society and Cooperation Partners;

Baschirotto,  Andrea
Max Planck Institute for Physics, Max Planck Society and Cooperation Partners;

Kroha,  Hubert
Max Planck Institute for Physics, Max Planck Society and Cooperation Partners;

Richter,  Robert
Max Planck Institute for Physics, Max Planck Society and Cooperation Partners;

Kortner,  Oliver
Max Planck Institute for Physics, Max Planck Society and Cooperation Partners;

Zhu,  Junjie
Max Planck Institute for Physics, Max Planck Society and Cooperation Partners;

Wang,  Jinhong
Max Planck Institute for Physics, Max Planck Society and Cooperation Partners;

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Citation

Pipino, A., Matteis, M. D., Resta, F., Baschirotto, A., Kroha, H., Richter, R., et al. (2019). A 130 nm CMOS PLL for Phase-II ATLAS-MDT TDC. Proceedings of Science, 092.


Cite as: https://hdl.handle.net/21.11116/0000-0005-D6A3-1
Abstract
The high luminosity and interaction rate expected from the planned High Luminosity-Large Hadron Collider (HL-LHC) upgrade require a replacement and improvement of the ATLAS Muon-Drift-Tube (MDT) read-out electronics. This paper presents a Phase Locked Loop (PLL) intended to be used inside the improved Time-to-Digital Converter (TDC), which digitizes the arrival time and charge amplitude information. Starting from a 40 MHz input clock, the PLL provides output clocks of 160 MHz and 320 MHz with a phase resolution of 11.25° and 22.5°, respectively. The prototype, integrated in 130 nm CMOS technology, has 0.02mm2 of area and 1.2 V of supply voltage.