Integration of III-V on silicon gain devices at the backside of 
silicon-on-insulator wafers for photonic fully integrated circuits

Menezo, Sylvie; Thiessen, Torrey; Mak, Jason; Da Fonseca, Jérémy; Ribaud, Karen; Yon, Zheng; Poon, Joyce

doi:10.1364/CLEO_SI.2020.SM4J.7

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Conference Paper

Integration of III-V on silicon gain devices at the backside of silicon-on-insulator wafers for photonic fully integrated circuits

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Mak, Jason
Nanophotonics, Integration, and Neural Technology, Max Planck Institute of Microstructure Physics, Max Planck Society;

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Poon, Joyce
Nanophotonics, Integration, and Neural Technology, Max Planck Institute of Microstructure Physics, Max Planck Society;

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https://doi.org/10.1364/CLEO_SI.2020.SM4J.7
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Citation

Menezo, S., Thiessen, T., Mak, J., Da Fonseca, J., Ribaud, K., Yon, Z., et al. (2020). Integration of III-V on silicon gain devices at the backside of silicon-on-insulator wafers for photonic fully integrated circuits. In CLEO: Science and Innovations 2020. doi:10.1364/CLEO_SI.2020.SM4J.7.

Cite as: https://hdl.handle.net/21.11116/0000-0008-1D02-6

Abstract

We present a new platform integrating heterogeneous III-V/silicon gain devices at the backside of silicon-on-insulator wafers. The fabrication relies on commercial silicon photonic processes. The performances of lasers and SOAs fabricated accordingly are reported.