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  Integration of III-V on silicon gain devices at the backside of silicon-on-insulator wafers for photonic fully integrated circuits

Menezo, S., Thiessen, T., Mak, J., Da Fonseca, J., Ribaud, K., Yon, Z., et al. (2020). Integration of III-V on silicon gain devices at the backside of silicon-on-insulator wafers for photonic fully integrated circuits. In CLEO: Science and Innovations 2020. doi:10.1364/CLEO_SI.2020.SM4J.7.

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Item Permalink: https://hdl.handle.net/21.11116/0000-0008-1D02-6 Version Permalink: https://hdl.handle.net/21.11116/0000-0009-4FCB-B
Genre: Conference Paper

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14016.pdf (Publisher version), 351KB
 
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https://doi.org/10.1364/CLEO_SI.2020.SM4J.7 (Publisher version)
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 Creators:
Menezo, Sylvie1, Author
Thiessen, Torrey1, Author
Mak, Jason2, Author
Da Fonseca, Jérémy1, Author
Ribaud, Karen1, Author
Yon, Zheng1, Author
Poon, Joyce2, Author           
Affiliations:
1External Organizations, ou_persistent22              
2Nanophotonics, Integration, and Neural Technology, Max Planck Institute of Microstructure Physics, Max Planck Society, Weinberg 2, 06120 Halle, DE, ou_3287471              

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 Abstract: We present a new platform integrating heterogeneous III-V/silicon gain devices at the backside of silicon-on-insulator wafers. The fabrication relies on commercial silicon photonic processes. The performances of lasers and SOAs fabricated accordingly are reported.

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Language(s): eng - English
 Dates: 2020-05-10
 Publication Status: Published online
 Pages: 2
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 Identifiers: DOI: 10.1364/CLEO_SI.2020.SM4J.7
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Title: Conference on Lasers and Electro-Optics (CLEO)
Place of Event: Washington, DC United States
Start-/End Date: 2020-05-10 - 2020-05-15

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Title: CLEO: Science and Innovations 2020
Source Genre: Proceedings
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Pages: - Volume / Issue: - Sequence Number: SM4J.7 Start / End Page: - Identifier: ISBN: 978-1-943580-76-7