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  Co-Design for Energy Efficient and Fast Genomic Search: Interleaved Bloom Filter on FPGA

Knaust, M., Seiler, E., Reinert, K., & Steinke, T. (2022). Co-Design for Energy Efficient and Fast Genomic Search: Interleaved Bloom Filter on FPGA. In FPGA '22 (pp. 180-189). New York, NY: Association for Computing Machinery. doi:10.1145/3490422.3502366.

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Proceedings FPGA22_Knaust et al_2022.pdf (Publisher version), 2MB
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Proceedings FPGA22_Knaust et al_2022.pdf
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 Creators:
Knaust, Marius , Author
Seiler, Enrico1, Author                 
Reinert, Knut2, Author                 
Steinke, Thomas, Author
Affiliations:
1IMPRS for Biology and Computation (Anne-Dominique Gindrat), Dept. of Computational Molecular Biology (Head: Martin Vingron), Max Planck Institute for Molecular Genetics, Max Planck Society, ou_1479666              
2Efficient Algorithms for Omics Data (Knut Reinert), Max Planck Fellow Group, Max Planck Institute for Molecular Genetics, Max Planck Society, ou_2385698              

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Free keywords: sequence alignment, indexing, FPGA, energy efficiency, performance
 Abstract: Next-Generation Sequencing technologies generate a vast and exponentially increasing amount of sequence data. The Interleaved Bloom Filter (IBF) is a novel indexing data structure which is state-of-the-art for distributing approximate queries with an in-memory data structure. With it, a main task of sequence analysis pipelines, (approximately) searching large reference data sets for sequencing reads or short sequence patterns like genes, can be significantly accelerated. To meet performance and energy-efficiency requirements, we chose a co-design approach of the IBF data structure on the FPGA platform. Further, our OpenCL-based implementation allows a seamless integration into the widely used SeqAn C++ library for biological sequence analysis. Our algorithmic design and optimization strategy takes advantage of FPGA-specific features like shift register and the parallelization potential of many bitwise operations. We designed a well-chosen schema to partition data across the different memory domains on the FPGA platform using the Shared Virtual Memory concept. We can demonstrate significant improvements in energy efficiency of up to 19 times and in performance of up to 5.6 times, respectively, compared to a well-tuned, multithreaded CPU reference.

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Language(s): eng - English
 Dates: 2022-02-11
 Publication Status: Published online
 Pages: -
 Publishing info: -
 Table of Contents: -
 Rev. Type: -
 Identifiers: DOI: 10.1145/3490422.3502366
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Title: FPGA '22: Proceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
Place of Event: Virtual Event
Start-/End Date: 2022-02-27 - 2022-03-01

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Title: FPGA '22
Source Genre: Proceedings
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Publ. Info: New York, NY : Association for Computing Machinery
Pages: - Volume / Issue: - Sequence Number: - Start / End Page: 180 - 189 Identifier: ISBN: 978-1-4503-9149-8