Help Privacy Policy Disclaimer
  Advanced SearchBrowse





Beyond the finite in automatic hardware verification


Basin,  David
Programming Logics, MPI for Informatics, Max Planck Society;

External Resource
No external resources are shared
Fulltext (restricted access)
There are currently no full texts shared for your IP range.
Fulltext (public)

(Any fulltext), 413KB

Supplementary Material (public)
There is no public supplementary material available

Basin, D., & Klarlund, N.(1996). Beyond the finite in automatic hardware verification (MPI-I-1996-2-009). Saarbrücken: Max-Planck-Institut für Informatik.

Cite as: https://hdl.handle.net/11858/00-001M-0000-0014-9FDC-F
We present a new approach to hardware verification based on describing circuits in Monadic Second-order Logic MSL. We show how to use this logic to represent generic designs like n-bit adders, which are parameterized in space, and sequential circuits, where time is an unbounded parameter. MSL admits a decision procedure, implemented in the MONA tool, which reduces formulas to canonical automata. The decision problem for MSL is non-elementary decidable and thus unlikely to be usable in practice. However, we have used MONA to automatically verify, or find errors in, a number of circuits studied in the literature. Previously published machine proofs of the same circuits are based on deduction and may involve substantial interaction with the user. Moreover, our approach is orders of magnitude faster for the examples considered. We show why the underlying computations are feasible and how our use of MONA generalizes standard BDD-based hardware reasoning.